The present invention relates to a method of manufacturing a semiconductor wafer, and more particularly to a low-cost method of manufacturing a high-quality silicon wafer.
Many processing steps are required to produce a silicon wafer from raw electrical-grade silicon. Ordinarily, a wafer manufacturing process includes processes for at least (1) forming a silicon single crystal from the raw silicon, (2) cutting a wafers from the crystal, (3) lapping and grinding the wafer, (4) etching the wafer to remove damage from the wafer surfaces, and (5) polishing and cleaning the wafer.
Each of these processes generally comprises numerous discrete steps. For example, the silicon crystal formation process requires first melting raw silicon in a crucible under an inert atmosphere, then pulling the crystal from the melt, and then shaping the crystal. Each of these individual steps may be quite slow, and can contribute significantly to the overall expense of manufacturing a wafer. For example, melting the silicon involves the relatively time-consuming steps of pumping down the pulling chamber and heating the crucible.
The crystal formation process contributes to the overall costs of manufacturing wafers in other ways as well. For example, the crucible from which the crystal is pulled is degraded by exposure to the silicon melt, and is typically rendered unsuitable for use after the pulling of only one or two crystals. Thus, the crucibles must be changed regularly. Changing the crucibles requires exposing the inside of the pulling system to the external atmosphere while the crucible is being changed, thus possibly necessitating later time-consuming outgassing and purging steps.
Other stages contribute to the cost of the wafer manufacturing process in a number of different ways. For example, the edge-shaping process may comprise several individual edge-grinding steps, depending upon the profile given to the edge. A beveling process may comprise three separate grinding steps: one for beveling each corner of the edge, and one for smoothing the remaining central portion of the edge. The greater the number of individual grinding steps needed, the greater the cost of the overall manufacturing process. As another example, a typical HF/HNO3 wafer etching process poses costs in the form of high-purity reagents and fluorine and nitrate waste disposal.
The above-described steps are used in essentially every silicon wafer manufacturing process. Sometimes, however, a wafer is desired that has enhanced physical properties relative to ordinary wafers. In these situations, the wafer must undergo additional processing steps that further increase manufacturing costs. For example, the wafer may undergo a thermal cycling process to form intrinsic gettering sites. During the crystal pulling process, oxygen from the walls of the quartz or fused silica crucible dissolves into the silicon melt as the crucible wall degrades. This oxygen, via the thermal cycling process, can be intentionally precipitated from the bulk silicon in regions away from device regions of the wafer to create gettering sites within the wafer bulk. Generally, the thermal cycling process is a three-step process. First, a high-temperature step is used to remove oxygen from the surface regions of the wafer, where it can harm circuit performance. Next, a lower temperature step is used to nucleate the oxygen precipitates. Finally, another high-temperature step is used to increase the size of the precipitates to create lattice strain.
The wafer may also be subjected to additional processes to create extrinsic gettering sites on the wafer backside. The creation of extrinsic gettering sites generally involves the creation of damage or stress in the backside of the wafer, which causes defects that can trap mobile impurities to form in the silicon lattice. Commonly used processes for damaging the wafer backside include sandblasting, grooving and abrading the wafer backside. The use of these extrinsic gettering techniques is not particularly desirable, as they may cause the contamination of the wafer. Another extrinsic gettering technique involves depositing a film of polycrystalline silicon on the back of the wafer via LPCVD. The grain boundaries and lattice defects in the polycrystalline silicon film act as gettering sites. Though this technique poses less of a danger of contamination, it requires the addition of an additional LPCVD step to the wafer manufacturing process, further increasing the cost of the overall process.
As another example of a process that increase the cost of wafers, some circuit fabrication processes may require wafers with precisely engineered electrical properties. In these instances, a precisely doped epitaxial film may be grown on the frontside of the wafer to give the wafer, commonly known as an epitaxial wafer, the desired electrical properties. The epitaxial deposition process consists of several individual steps. First, the backside of the wafer is usually sealed with an SiO2 film to prevent any wafer dopants or impurities on the wafer backside from contaminating the growing epitaxial film. The SiO2 film is typically deposited via an LPCVD process that includes pumpdown, heating, deposition and cooling steps. Next, the wafer is placed in an epitaxial deposition chamber for the epitaxial deposition process. This process also has pumpdown, heating, deposition and cooling steps. Thus, the deposition of the epitaxial layer requires two entire deposition cycles: one for the backseal process and one for the epitaxial deposition. These cycles each add additional time and expense to the wafer manufacturing process, and may make the resulting wafer prohibitively expensive for potential users. Finally, sometimes the oxide film must be removed from the wafer backside before the wafers can be used for circuit fabrication. The film is usually removed with an HF stripping process, adding even more costs to the manufacturing process.
The cost of the wafer manufacturing process increases with each additional step used. Because high-quality wafers require more manufacturing steps than ordinary wafers, they may be too expensive for use in some applications where they may otherwise be desirable. Thus, there remains a need for a lower-cost method of manufacturing a high quality wafer, and in particular an epitaxial wafer.
One aspect of the present invention provides a method of manufacturing a silicon wafer. The method comprises providing a crucible for melting silicon; adding silicon to the crucible; melting the silicon to form a melt; applying an electrical potential across the crucible; pulling a silicon crystal from the melt according to the Czochralski technique at a pulling rate of greater than 1.1 mm/min; and forming a silicon wafer from the silicon crystal. The method may also include simultaneously depositing an epitaxial first film on the frontside of the wafer and a second film on the backside of the wafer, wherein the second film traps impurities on the backside of the wafer so the impurities do not contaminate the frontside of the wafer while the epitaxial first film is being grown. Furthermore, the method may also include adding a nitrogen-containing dopant to the crucible.
Another aspect of the present invention provides a method of manufacturing a silicon wafer. The method comprises forming a silicon crystal; forming a silicon wafer from the silicon crystal, the wafer having a frontside, a backside and an edge; rounding the edge of the wafer; etching the wafer in an alkaline etching solution; immersing the wafer in an acidic etching solution after etching the wafer in the alkaline etching solution; and simultaneously depositing an epitaxial first film on the frontside of the wafer and a second film on the backside of the wafer, wherein the second film traps impurities on the backside of the wafer so the impurities do not contaminate the frontside of the wafer. The method may also include adding a nitrogencontaining dopant to the crucible.